Senior/Staff Design for Test Engineer

ABOUT OLIX AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance. THE ROLE We are seeking highly skilled and motivated Senior/Staff DFT (Design for Test) Engineers with a strong focus on high-performance digital design to take end-to-end ownership of robust, testable silicon, from early test strategy definition to verified DFT implementation, pattern generation, and silicon bring-up. You will join a multidisciplinary group creating next-generation accelerators where digital, optical, and mixed-signal domains intersect. The ideal candidate will have extensive experience in the DFT of large-scale, high-volume ASICs and a passion for developing reliable, high-coverage test architectures that drive breakthrough AI hardware RESPONSIBILITIES - Architect, own, and implement the comprehensive Design-for-Test (DFT) strategy for complex high-throughput digital pipelines in advanced CMOS nodes, ensuring high test coverage and efficient test execution. - Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST, ensuring adherence to industrial standards and sign-off criteria. - Partner with the test engineering team to develop, validate, and optimize ATE-compatible test patterns (stuck-at, transition, bridging, etc.) to achieve aggressive fault coverage and maximise manufacturing yield. - Drive RTL development (SystemVerilog / Verilog / VHDL) with a focus on DFT architecture, including synthesis constraints for test structures, and collaborate on formal and constrained-random verification of DFT logic. - Analyse and minimise the DFT impact on power, performance, and area (PPA), implementing innovative techniques for efficient test access and execution. - Collaborate with mixed-signal and software teams to define and optimise DFT interfaces, test modes, and firmware abstractions for test control and diagnosis. - Mentor junior engineers, lead DFT design reviews, and champion best-practice methodologies for testability and debug across the ASIC development lifecycle. SKILLS & EXPERIENCE - 7+ years of hands‑on DFT architecture, implementation, and verification for high‑performance ASICs or SoCs, including ownership of at least one product with comprehensive DFT coverage. - Proven success implementing and verifying advanced DFT features (e.g., Scan/ATPG, Boundary Scan, Memory BIST/Repair) on multi‑hundred‑MHz to multi‑GHz clock domains. - Expertise with industry‑standard EDA flows: Scan insertion, ATPG, pattern simulation (gate-level), fault modeling, and diagnosis tools. - Demonstrated proficiency with DFT flows: compression techniques, EDT, JTAG/IEEE 1149.1/1687, and managing large pattern sets. - Proficiency using Python/Tcl scripting for DFT flow automation, pattern generation/management, and silicon debug/bring-up. - Solid grounding in semiconductor device physics, fault models (stuck-at, transition, bridging), and yield enhancement strategies. - Excellent communication and cross‑functional collaboration abilities; thrives in a fast‑moving, ambiguous environment. NICE TO HAVE - Tape‑out experience at 22 nm or below. - Knowledge of high-speed SerDes or HBM/DDR DFT challenges. - Familiarity with AI/ML workloads or systolic arrays and their implications for DFT. - Contributions to open‑source DFT tools or verification frameworks. COMPENSATION & EQUITY - Competitive Sa