Physical Design Engineer

ABOUT OLIX AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance. THE ROLE We are seeking highly skilled and motivated Senior/Staff Engineer with experience in both Physical Design and Digital Circuit Design. This role will work closely with our Analog design team to design and implement digital control logic solutions that will be integrated directly into our analog subsystem. The tight integration of high-performance digital solutions with custom analog/RF circuits will require customizing our design environment to meet the unique requirements posed by this mixed analog/digital subsystem. You will join a multidisciplinary group creating next-generation accelerators where digital, optical and mixed-signal domains intersect. The ideal candidate will have extensive experience in the implementation of high-performance digital solutions and strong understanding of the unique aspects of analog designs that will be impacted by the integration of digital circuits. RESPONSIBILITIES - Architect, own, and implement the digital control solutions require to support the operation of our high-performance analog subsystem. - The very close integration of these digital solutions into the analog subsystem will require customized physical design solutions across many aspects of the physical design space: - Low-power and low-skew clock distribution network constructed with greatly reduced metal stack usage - Power grid implementations customized to the unique floorplan requirements of the analog subsystem - Multi-voltage-domain design flows to support the different power rails used within the analog solution - Timing analysis for interfaces with the analog subsystem - DRC/LVS/ERC validation and closure of advanced-node processes - Collaborate with the DFT team to implement customized DFT flow SKILLS & EXPERIENCE - 7+ years of hands‑on with architecture, implementation, and verification of the Physical Design for high‑performance ASICs or SoCs. - Proven success implementing and verifying the physical design of high-frequency designs in advanced process nodes. - Proficiency using Python/TCL scripting for PD flow automationExcellent communication and cross‑functional collaboration abilities; thrives in a fast‑moving, ambiguous environment. NICE TO HAVE - Tape‑out experience with process nodes at 7nm or below. - Familiarity with the integration of high-speed IO solutions like PCIe SerDes PHY solutions - Familiarity of the ESD requirements of advanced node processes COMPENSATION & EQUITY - Competitive Salary: Commensurate with your experience, skills, and location - Equity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it - Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office - Retirement Benefits: Employer-contributed retirement plans to help you build long-term financial security Due to U.S. export control regulations, candidates’ eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau