Staff FPGA Engineer

ABOUT OLIX AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance. THE ROLE We are seeking a highly experienced Staff FPGA Engineer to lead the architecture, design, and technical direction of FPGA-based systems within our platform. This is a senior individual contributor role focused on system-level ownership, cross-functional technical leadership, and architectural decision-making. You will define high-performance FPGA subsystems spanning high-speed interfaces, precision timing and synchronisation, transceivers, and signal processing pipelines. You will work closely with ASIC, hardware, optical, and software teams to drive coherent system design, de-risk silicon development, and deliver production-grade solutions. RESPONSIBILITIES - Define and own FPGA architecture for high-performance, high-bandwidth systems. - Lead design and optimisation of high-speed interface subsystems (PCIe Gen4, multi-lane transceivers operating at >25 Gb/s NRZ). - Architect deterministic timing and synchronisation strategies across complex multi-device systems. - Drive FPGA-based prototyping efforts to support silicon development and system validation. - Establish design methodologies, coding standards, and verification strategies. Guide implementation of robust error detection and correction mechanisms (ECC, including SECDED). - Partner with software teams to define hardware–software interfaces and system control models. - Lead system-level debugging of complex hardware–software interactions. - Mentor engineers and provide technical leadership across FPGA development efforts. - Identify performance bottlenecks and drive architectural improvements. - Maintain deep awareness of advancements in FPGA architectures and high-speed digital design. SKILLS & EXPERIENCE - 8+ years of FPGA design experience, including significant experience in high-speed digital systems. - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. - Proven experience architecting PCIe, Ethernet, RoCEv2 RDMA, and high-speed transceiver-based systems. - Deep expertise in precision timing, deterministic networking, and synchronisation architectures (experience with White Rabbit strongly valued). - Strong background in signal processing pipelines implemented in FPGA. - Experience supporting ASIC prototyping or silicon validation via FPGA platforms. - Advanced verification experience (COCOTB, UVVM, OSVVM, or equivalent methodologies). - Expert-level proficiency in Verilog and/or VHDL. - Strong Python and scripting skills for tooling and automation. - Experience with Xilinx/AMD UltraScale+, Versal, or Intel Agilex 7 architectures. - Demonstrated ability to lead technical direction without formal management authority. - Strong system-level debugging and performance optimisation experience. WHAT WE'RE LOOKING FOR - A systems thinker who operates comfortably at architectural altitude. - A technical leader who raises the bar across design quality, performance, and reliability. - Someone who thrives in ambiguity and drives clarity across multidisciplinary teams. - A hands-on expert who can move between architecture and implementation when needed. COMPENSATION & EQUITY - Competitive Salary: Commensurate with your experience, skills, and location - Equity & Ownership: Meaningful stock options. You’re not just joining the mission; yo