Senior Runtime Software Engineer

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Sydney, Australia, office 3 days per week. The role: Senior Runtime Software Engineer What you will do: d-Matrix is developing an AI inference processor for accelerating the inference of NLP, vision, and recommendation workloads in a data center environment. The architecture uses an in-memory compute processor subsystem, with a mix of fixed-point and floating-point data types in both dense and sparse matrix processing modes. During the seed round, the company has developed a CMOS test chip and validated the architecture using real inference workloads compiled from PyTorch. The position is a runtime SW engineer to work on the architecture and development and validation of the functionality and efficiency of firmware/software that is executed on the system-on-chip’s multiple processors and low-level drivers and system programs that host this system-on-chip. In this role, you will be largely responsible for all aspects of runtime performance of the silicon product. You will architect, document, and develop the runtime firmware that executes in the various on-chip multi-core CPU subsystems. This firmware will be controlling all aspects of the AI subsystems in the chip and will be architected to maximize the utilization of the hardware. Measures of success will be overall AI hardware utilization, minimizing communication bottlenecks, and maximizing on-chip memory utilization. You will bring the software up on FPGA platforms (that contain images of the embedded CPU subsystems) and debug it using JTAG-connected IDE. You will develop a firmware solution that can be developed and tested ahead of the availability of the AI subsystem hardware. You will be responsible for determining the delivery schedule and ensuring the software meets d-Matrix coding and methodology guidelines. You will collaborate with the hardware teams (to interpret the hardware specifications and suggest changes that improve utilization and throughput and/or reduce power). You will collaborate with other members of the SW team (located in AU and the US) and the SW quality & test team (US and India), as well as the HW verification team (to assist with SoC-level DV simulations and emulation). You will be developing and debugging code on the FPGA-based systems containing CPU subsystems and SystemC models of the AI subsystems and SoC You will also be involved in porting the software to a “big iron” emulation system (e.g., Veloce, Palladium) containing the final RTL. You will also be closely involved in the bringing up of the software on the AI subsystem hardware and validating silicon and software performance. What you will bring: - BS/MS Preferred degree in computer science, computer engineering, or similar with a minimum of 5 years of industry experience in embedded software development - Experience with multi-threaded C programming on multi-core CPUs running an RTOS in both AMP and SMP configurations - Understanding of methods used to synchronize many-core and many-CPU architectures - Managing static resources without an MMU - Zephyr OS experience is an advantage - Experience with PIC programming and developing interrupt service routines - Knowledge of bootloaders and Linux device drivers is an advantage - Ability to interpret HW-centric data sheets and register definitions to determine how to best program the architecture - Ability to work w