Sr. ASIC DFT Engineer (Silicon)

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Run and debug non-timing and SDF annotated gate-level simulations Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++ BASIC QUALIFICATIONS: Bachelor’s degree in electrical engineering, computer engineering, or physics 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing PREFERRED SKILLS AND EXPERIENCE: Master’s or PhD in electrical engineering, computer engineering, physics, or related engineering field Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug Experience collaborating with cross-functional teams (e.g., design, verification, and manufacturing) to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low-power DFT techniques using Siemens Tessent Experience with In-System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics, preferably using Siemens Tessent tools Hands-on experience with Tessent Streaming Scan Network Experience with cell-aware fault models in ATPG Excellent problem-solving skills, with the ability to analyze complex test failures and implement corrective actions Strong communication skills for documenting test strategies, reporting results, and presenting to stakeholders Ability to work in a fast-paced environment, handling mult