Sr. Staff Engineer, RISC-V Software Workload Enablement

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly technical Senior Staff/Principal Engineer to lead the porting and enablement of critical AI workloads. You will be a primary driver in migrating compute workloads to RISC-V architectures, ensuring our hardware is optimized for real-world application performance. The ideal candidate has a strong background in DevOps, workload porting, or application enablement . While this is an individual contributor role at its core, you will have the opportunity to grow and lead a small, specialized team over time as our workload migration efforts scale. This role is remote, based in the United States or Australia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A Technical Catalyst: You thrive on the challenge of driving AI hardware porting to RISC-V and making complex software stacks run efficiently on new hardware. Systems Expert: You possess deep knowledge of system software, compilers, or low-level OS internals. You are an expert in ARM or x86 environments and are ready to apply those skills to the RISC-V frontier. A Project Driver: You have the technical authority to lead the implementation of a compute migration to RISC-V through strategic IT and DevOps enablement. Collaborative & Cross-Functional: You enjoy acting as the "technical glue" between IT, DevOps, and AI teams , coordinating complex efforts across boundaries to ensure seamless workload transitions. Architecture Agnostic: You are a systems thinker who understands how to bridge the gap between infrastructure and core silicon engineering. What We Need Education: BS/MS/PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field. Workload Expertise: Extensive experience in workload porting, DevOps engineering, or application enablement . Systems Fluency: Strong familiarity with CPU architectures and systems design, with a proven track record of troubleshooting and optimizing performance across new architectures. Leadership Qualities: Ability to coordinate across multiple technical teams and the potential to mentor or grow a small engineering pod. Execution Focus: A mindset geared toward technical delivery and methodology development rather than broad community networking. What You Will Learn Gain deep expertise in bleeding-edge RISC-V system software across server and AI-accelerated environments. Directly influence an upcoming project , a high-visibility initiative shaping the future of our internal compute infrastructure. Work at the intersection of AI/ML workloads and hardware/software co-design. Shape the technical roadmap for how the industry adopts RISC-V for high-performance compute. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administra