Power Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. This is a CPU tech-leadership role focused on driving power analysis and projections for the development of CPU chiplet with an emphasis on power analysis. The role involves defining CPUrail planning while collaborating closely with SoC and Board teams. Responsibilities include optimizing the system PDN for Block rails, and managing the power vector plan for comprehensive coverage of Chip level. The position requires driving power analysis on RTL and Netlist using tools like Joules and PrimePower, working with RTL design, synthesis, and physical design teams to measure and optimize power, and evaluating new power optimization techniques at various design stages. Additionally, the role involves tabulating metrics results for analysis comparison and workingwith post-silicon teams to correlate projections with silicon power measurements. This role is hybrid, based out of Tokyo, Japan We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Extensive experience in power analysis and optimization for complex ASICs (typically 10+ years of ASIC or related design experience). Comfortable working across RTL, synthesis, and physical design stages, including low‑power implementation techniques and ECO‑based timing closure. Proficient with power analysis tools (e.g., Joules, PrimePower) and scripting (Tcl plus at least one of Python or similar). Strong analytical and problem‑solving skills, with clear written and verbal communication when collaborating across SoC, board, and post‑silicon teams. Nice to have: familiarity with UPF/CPF low‑power intent, Verilog/SystemVerilog, CPU micro‑architecture and its power challenges, and basic thermal analysis. What We Need Own power analysis and projections for the CPU chiplet, with emphasis on defining and tracking power metrics throughout the design cycle. Define and maintain the power vector plan for comprehensive chiplet‑level and chip‑level coverage. Drive power analysis on RTL and netlist using tools such as Joules and PrimePower, partnering with RTL design, synthesis, and physical design teams to measure and optimize power. Evaluate and propose new power optimization techniques at RTL, synthesis, and physical design stages, and implement changes via timing ECO and flow updates. Tabulate and compare power metrics and reports across design iterations, and work with post‑silicon teams to correlate projections with silicon measurements. What You Will Learn How to define and execute a power strategy for a 2nm CPU chiplet within a multi‑chiplet system‑in‑package, including rail planning and system‑level PDN optimization. Best practices for end‑to‑end power closure, from RTL through netlist and physical design, in collaboration with global RTL, SoC, and board teams. How to correlate pre‑silicon power models with real silicon behavior and feed less