Senior Physical Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a senior physical design engineer to join Tenstorrent’s AIDC Yayoi project, driving chiplet-level and chip-top physical implementation of high-performance CPU-based SoCs in a cutting-edge system-in-package environment. This role is hybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have a Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or computer science, with extensive experience (typically 10+ years) in SoC/ASIC/GPU/CPU physical design on taped-out designs. You are highly skilled with industry-standard tools (e.g., Synopsys/Cadence) and physical verification, and comfortable scripting in TCL and at least one other language (e.g., Python). You are a strong collaborator who can guide and mentor junior engineers, communicate clearly with global stakeholders, and navigate complex technical trade-offs to drive designs to closure. You are organized and data-driven, able to build implementation plans, monitor PPA and schedule metrics, communicate resource needs, and proactively identify and manage risks. What We Need Lead chiplet and chip-top implementation for a high-profile, multi-chiplet System-in-Package project and place and route for high-speed CPU core designs in advanced nodes (5nm and below). Own chip-top floorplanning and integration: BUS and fabric planning, bump and IO placement, and hierarchical top/bottom floorplanning to achieve timing and PPA closure at chip level. Drive full physical verification and convergence, electrical rules, DRC/LVS, noise, and electromigration checks Take ownership of chip-level synthesis, BUS and bump planning, SoC floorplanning, and chip-top PV and EMIR, while providing technical leadership and mentoring to junior team members. What You Will Learn Deep expertise in system-in-package design and multi-chiplet integration, working hands-on project with complex chip-top interfaces and constraints. Best practices for high-frequency, advanced-node (5nm and below) CPU design implementation, including cutting-edge timing closure, EMIR, and sign-off methodologies. How to operate in a highly collaborative global environment, partnering daily with Tenstorrent experts and leaders across Japan, the USA, and other regions, as well as external stakeholders. Advanced strategies for scaling physical design flows, improving reproducibility of convergence, and optimizing project PPA and schedule across multiple tapeouts. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups