Advanced Packaging Process Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an Advanced Packaging Process Engineer with experience in 2.5D and 3D chiplet packaging to join Tenstorrent’s Packaging team. You will drive advanced package technology and reliability in close partnership with foundries and OSATs, helping push performance and manufacturability for next‑generation AI/ML products. This role is hybrid, based out of Santa Clara, CA or Taipei City, TW. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are Advanced packaging engineer with hands-on 2.5D/3D experience (CoWoS-R/L, FOCoS, EMIB, FCBGA, organic substrates, silicon interposers, embedded Si/eCB, micro-bumps, BGAs). Strong in reliability and failure analysis for advanced packaging, including qualification, root cause analysis, and corrective actions. Deep understanding of process flows and materials (polyimide, ABF, core, underfill, mold compound) and their interactions (warpage, stress, delamination, mechanical risk). Proven track record working with foundries/OSATs on NPI, design rules, excursions, yield/cost optimization, and production ramp, with clear communication and cross-functional collaboration. What we need Own advanced package technology implementation for 2.5D/3D chiplet products, including technology choices, process integration, and manufacturability. Act as primary technical interface to foundries/OSATs: align capabilities and design rules, manage excursions, drive yield, define/track test vehicles, and coordinate FA. Partner with design, reliability, and architecture teams to evaluate tradeoffs (bump pitch, stack-ups, embedded Si, etc.) and lead test vehicle planning to meet program needs. MS/PhD in a relevant field (Materials, Mechanical, Electrical, Physics, or related) and 5+ years in advanced packaging for high-performance semiconductors from NPI through production (2.5D/3D flows such as CoWoS, FOCoS, EMIB, FCBGA or equivalent). What you will learn Deeper exposure to leading-edge 2.5D/3D packaging for high-performance AI/ML and chiplet-based architectures. How to balance performance-driven architecture with mechanical and reliability constraints to make robust package technology decisions. Ways to use AI- and automation-driven methods to accelerate risk assessment, qualification planning, and technical documentation. Best practices for building strategic OSAT and foundry partnerships that enable new capabilities while scaling reliable high-volume production. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements appl