IC Package FEA Engineer

ABOUT LUMILENS At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing - faster, cooler, and massively more efficient. We’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry. At Lumilens, we’re developing high-speed photonics products purpose-built to power the future of AI infrastructure and high-performance computing. This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in scaling optical systems. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow. If you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started. POSITION OVERVIEW At Lumilens, we are redefining the optical layer that powers tomorrow’s AI and high‑performance computing. We are seeking an experienced IC Package Mechanical FEA Engineer to help drive the next generation of high‑performance packaging solutions for advanced ASICs. In this role, you will join a globally distributed R&D organization developing mechanical designs that enable cutting‑edge systems for AI, networking, HPC, and 5G infrastructure. You will work hands‑on with emerging packaging and photonic‑integration technologies, including co‑packaged fiber‑optic transceivers, novel optical connectors, and complex chip‑stacking approaches such as 3DIC, hybrid copper bonding, and heterogeneous integration. You will design, model, and optimize advanced multi‑chip‑module (MCM) architectures and mainstream flip‑chip BGA (FCBGA) packages to support Lumilens’ high‑speed photonic engines. Collaboration is central to this role: you will partner closely with R&D, manufacturing, and reliability teams to influence ASIC mechanical design from the earliest stages. Your engineering decisions will directly impact warpage, stress, reliability, cost, and overall thermal and electrical performance, ultimately shaping the photonics infrastructure that fuels future AI supercomputing. Requirements: - Bachelor’s in Mechanical Engineering (or related field) with 12+ years FEA experience, Master’s with 10+, or PhD with 7+. - Deep expertise in advanced packaging technologies, including flip‑chip, FOWLP, 2.5D/3D integration, chiplet architectures, and TSVs. - Strong understanding of materials behavior across polymers, metals, ceramics, and their thermo‑mechanical interactions. - Familiarity with semiconductor packaging processes such as die attach, underfill, molding, bumping, and reflow. - Proficiency with FEA tools, including Ansys Classic/Mechanical and Abaqus. - Ability to interpret and correlate complex simulation results using first‑principles mechanical engineering concepts. - Demonstrated experience calibrating models with empirical data, including hands‑on mechanical testing and metrology. - Proven capability in developing and running lab‑level experiments to validate simulations and identify root causes. - Strong judgment in balancing manufacturing constraints, reliability requirements, and performance needs. - Excellent self‑management, organizational discipline, and ability to thrive in a fast‑moving environment. - Comfortable collaborating with global, cross‑functional engineering teams and external vendors. - Strong presentation, communication, and technical documentation skills. Responsibilities: - Perform FEA simulations to evaluate stress, strain, warpage, delamination, thermal cycling, and reliability risks across advanced package architectures (flip‑chip, fan‑out, 2.5D/3D IC, chiplet‑based, TSVs). - Define simulation requirements, analyse results, and deliver