Senior/Principal Signal Integrity Engineer-Silicon Photonics & AI Interconnects

ABOUT LUMILENS At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.We’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry. This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow. If you're looking for mission, momentum, and the chance to make an outsized impact jump on the rocket ship. We’re just getting started. About the Role Lumilens is revolutionizing AI compute infrastructure with next-generation photonic interconnects. Our solutions—leveraging co-packaged optics (CPO), near-packaged optics (NPO), high-density silicon photonics, and advanced heterogeneous integration—enable massive scale-out and scale-up architectures for the world's leading AI providers. We are seeking a world-class Senior / Principal Signal Integrity Engineer to own and drive signal integrity (SI) and closely related power delivery strategies across complex 2.5D/3D packages. These packages integrate electrical ICs, photonic ICs, chiplets, and high-bandwidth memory, where electrical interconnects must support ultra-high-speed data paths while coexisting with optical interfaces. In this high-impact role, you will lead end-to-end SI analysis and optimization for cutting-edge photonic-electronic systems, influencing architecture from concept through production. Key Responsibilities: - Perform detailed electromagnetic (EM) modeling, extraction, and simulation of advanced packages, including silicon interposers, bridges, 2.5D/3D stacks, fan-out, CoWoS-like, and EMIB-like structures. - Conduct comprehensive end-to-end high-speed channel analysis for analog circuits, SerDes (PAM4/NRZ at 100G+/lane), parallel buses, UCIe die-to-die links, and hybrid electrical-optical interconnects. - Develop and optimize package stack-ups, routing strategies, via transitions, bump pitch/layout, and redistribution layers (RDL) to minimize insertion/return loss, crosstalk, mode conversion, and impedance discontinuities. - Collaborate closely with silicon, photonic IC, and system design teams on bump map/pinout optimization, die-to-package co-design, floorplanning, and meeting SI targets across CMOS, BiCMOS and photonic processes. - Execute pre- and post-layout SI simulations with industry-standard tools to predict performance, identify risks, and recommend mitigations (e.g., equalization techniques, redundancy, material choices). - Establish SI design rules, guidelines, and best practices for advanced packaging in photonic-integrated systems, ensuring adoption across projects. - Partner with lab teams to correlate simulations with high-frequency measurements (VNA, TDR/TDT, oscilloscopes, BERTs) on test vehicles, including de-embedding of fixtures and launch structures. - Work with power integrity (PI) engineers on concurrent SI/PI analysis, including SSO, PDN resonance effects on high-speed signals, and decap optimization in dense photonic-electronic packages. - Lead technical reviews, present SI/PI findings to cross-functional stakeholders (technical and non-technical), and drive timely closure of design issues. - Contribute to methodology advancements for emerging technologies, including optical interconnects, glass-core substrates, wafer-/panel-level packaging, and CPO/NPO architectures. Required Qualifications: - Bachelor's or Master's degree in Electrical Engineering, Physics, or related field (PhD preferred). - 10+ years of relevant experience in high-speed SI/PI, w