Signal Integrity Engineer-1.6 OSFP Board Design

Signal Integrity Engineer –1.6T OSFP Board Design Bengaluru, Karnataka, India / Onsite ABOUT LUMILENS At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient. We’re a well-funded startup backed by Mayfield and led by veterans who’ve built And scaled some of the most transformative technologies in the industry. This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some ofthe hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow. If you're looking for mission, momentum, and the chance to make an outsized impact jump on the rocket ship. We’re just getting started. Role Overview We are seeking a Signal Integrity (SI) Engineer with 6–10 years of experience to own board-level high‑speed electrical design for 1.6T DR8 (200G/lane) OSFP optical modules, from pre‑layout simulations through validation and production support. Key Responsibilities: - Own SI/PI design for 1.6T DR8 OSFP module host and line‑side interfaces, including 200G PAM4 lanes, DSP/ASIC interfaces, retimer/gearbox and connector transitions on the module PCB - Perform pre‑ and post‑layout SI simulations (time and frequency domain) for very high‑speed channels: insertion/return loss, crosstalk, impedance, eye diagrams, COM and bathtub analysis. - Define PCB stack‑up, materials, via technology, routing rules and design constraints to meet loss budgets and margin targets at 200G per lane within OSFP mechanical constraints. - Generate clear SI/PI design guidelines for schematic and layout engineers; review schematics and layout (diff‑pair routing, reference transitions, stitching, breakouts) and sign off on SI. - Collaborate closely with optical, mechanical, firmware and test teams on overall 1.6T module architecture, pin‑outs, power partitioning and control interfaces. - Plan and execute lab bring‑up and correlation: TDR, VNA/S‑parameter measurements, eye/PAM4 analysis, jitter decomposition and de‑embedding to validate and refine models. - Drive SI‑related root‑cause debug on proto and production builds, propose design changes and work with manufacturing/NPI to ensure robust, repeatable performance. - Contribute to technical documentation: SI test plans, simulation reports, design guidelines, and lessons‑learned for future OSFP generations. Required Qualifications: - ⁠B.E/B.Tech http://B.Tech or M.E/M.Tech http://M.Tech in Electrical/Electronics Engineering (or equivalent) with 6–10 years of experience in high‑speed board‑level design/SI for networking, server or optical module products. - Strong hands‑on experience with pre/post‑layout SI simulations on SerDes links ≥56G, ideally 100G/200G PAM4, using tools such as Sigrity, ADS, HFSS, SIwave, HSPICE or similar. - Proven track record defining PCB stack‑ups, materials (e.g., low‑loss laminates), via structures and routing rules for multi‑hundred‑Gbps interfaces on dense form‑factor modules or line cards. - Strong understanding of: transmission lines, S‑parameters, equalization (FFE/DFE/CTLE), jitter, crosstalk, return path design, reference plane design and power distribution networks. - Solid lab skills with high‑bandwidth scopes, VNAs, BERTs and TDRs, including fixture design/de‑embedding and correlation of measurements to simulations. - Experience working with cross‑functional teams (layout, optics, mechanical, FW, test, manufacturing) on complex hardware projects through multiple prototype spins. - Good written and verbal communication to clearly document constraints, justify design decisions and review results with stakeholders. Preferred Qualifications: - Experience specif