Head of Performance Visibility

About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are hiring a Head of Performance Visibility to define how performance is understood across next-generation AI accelerator systems. Our ML accelerator platform spans custom silicon, supercomputing software, compiler stacks, runtime libraries, and distributed inference environments. Performance at this scale is no longer a device-level question — it is a high-performance distributed system problem. You will define the performance metrics that connect raw hardware signals to distributed workload context, ML cluster dynamics, pod communication patterns, and emergent bottlenecks. This role requires more than telemetry. You will establish new abstractions, structured counter ontologies, cross-layer event correlation frameworks, distributed time-alignment strategies, and scalable reasoning systems operating across nodes, racks, and clusters. Working at the intersection of hardware design, driver architecture, runtime systems, and ML infrastructure, you will shape how these layers expose and consume performance intelligence. This is a foundational role defining not just tooling, but how our platform reasons about efficiency, scalability, and system behavior for years to come. Key Responsibilities besides Mentorship and Leadership System-Level Performance Design - Define the architectural approach for collecting and structuring telemetry across CPUs, drivers, interconnects, and multiple accelerators - Design scalable models for correlating performance events across device and host boundaries Cross-Layer Event Correlation - Develop mechanisms to align hardware counters, runtime activity, communication phases, and workload semantics across model-layer execution into coherent, actionable insight - Implement time synchronization and trace-alignment strategies across multi-device systems Telemetry & Counter Modeling - Define structured counter taxonomies separating base signals from derived metrics - Design derived performance models bridging low-level hardware signals and workload-level behavior - Influence instrumentation strategy for future hardware generations Distributed Performance Reasoning - Build tools that identify bottlenecks among multi-accelerator workloads across chips within hosts - Build cluster-scale performance analysis for distributed inference across data center networks Tooling & Insight Delivery - Contribute to analysis engines and developer-facing tooling that transform raw telemetry into intuitive insight - Shape how performance intelligence is surfaced to engineers debugging large-scale AI systems You may be a good fit if you have - Deep experience building complex systems at the intersection of hardware and software - Personally envisioned and built significant portions of profiling, tracing, or observability systems — not solely defined requirements or product strategy - Demonstrated ability to translate raw hardware signals into scalable, production-grade telemetry and analysis infrastructure - Experience correlating time-series events across distributed systems - Deep systems programming expertise (C++ or Rust), with a track record of shipping low-level infrastructure operating close to hardware or runtime systems - Experience designing distributed correlation mechanisms, timestamp-alignment strategies, or performance modeling frameworks across multiple devices or hosts - Experience designing distributed tracing or observability platforms at scale - E