ASIC Technical Program Manager

About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is seeking a highly skilled and motivated ASIC Technical Program Manager to join our silicon team. This is a hands-on, high-accountability role for someone who has lived inside the ASIC development cycle and can drive technical execution, not just track it. You will own program coordination across Physical Design, DFT, DV, and RTL teams while managing relationships with external vendors including IP providers, implementation partners, and EDA tool vendors. The ideal candidate has real tape-out experience, understands the full RTL-to-GDSII flow, and operates with the urgency and proactivity that a first-silicon program demands. Key Responsibilities - Cross-Functional Technical Coordination: Own program management across Physical Design, DFT, DV, RTL, and Post-Silicon teams. Understand inter-team dependencies - know who owns what, when handoffs need to happen, and what needs to be signed off before downstream work can begin (e.g., RTL version gates for synthesis, DFT insertion checkpoints, ECO cycles). - Vendor Management: Engage directly with external vendors, including EDA partners and implementation partners. Hold vendors accountable to timelines and deliverables. Be prepared to push back, defend Etched’s technical requirements, and escalate when needed. - Risk Identification and Mitigation: Proactively surface critical path risks, schedule slippage, and cross-team blockers. Develop mitigation strategies in partnership with engineering leads and escalate appropriately to technical and executive stakeholders. - Project Planning and Execution: Manage the scheduling and execution of complex, multi-team hardware programs. Keep projects on track across tape-out milestones, synthesis respins, and signoff cycles. - Stakeholder Communication: Provide regular, clear updates to engineering leads, VP-level stakeholders, and executive leadership on project status, risks, and decisions required. Set the tone for meetings, facilitate alignment, mediate technical disagreements, and drive to decisions. - Process Coordination: Work with ops and engineering teams to maintain accurate tracking of program state, action owners, and open items. Support the adoption of tooling and dashboards that improve engineering visibility - though dashboard creation itself sits with the ops team. - Technical Acumen: Bring enough ASIC domain knowledge to communicate credibly with engineers across the design stack and with external partners. You don’t need to be a designer, but you need to know the difference between a .3 and .5 RTL release, understand where DFT fits in the flow, and have a feel for what a synthesis restart actually involves. You may be a good fit if you have (Must-have qualifications) - At least one full ASIC tape-out under your belt. You should be able to speak fluently to what that process looks like end-to-end. - Solid understanding of the RTL-to-GDSII flow, including where Physical Design, DFT, DV, and RTL teams intersect and hand off to each other. - 5+ years of experience in technical program management, engineering program management, or a closely related role within the semiconductor or hardware space. - Experience working directly with external EDA vendors or implementation partners - you’ve been in those rooms and know how to hold your ground. - Exceptional follow-through and proactivity. You chase down dependencies; you don’t wait for them to surface. - Strong communic