Physical Design - Front End Lead

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution Efficient is seeking a Physical Design - Front End Lead to join our growing team. The ideal candidate would drive front-end PD methodology (Synthesis, LEC, CLP, Low Power Design) hands on. We believe in a correct-by-construction philosophy and place a great emphasis on ensuring frontend flows accurately model signoff considerations. The Front End lead will ensure that we have methodologies in place to ensure the design built considers the right tradeoff between timing and power and optimizes for both aspects. The role is cross functional and we are an integrated highly interdisciplinary team of world class engineers. This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond! Key Responsibilities Drive and develop frontend flows and methodology for the industry defining Energy efficient general purpose processors. Ensure synthesis flows accurately model all aspects of PPA to enable highly optimized and correct by construction design to enable tight and quick design loops and design convergence Develop LEC flows to continuously assess logical correctness of the design as the design progresses to mature thru the design lifecycle. Define UPF methodology and develop and converge UPF for all complex subsystems and SOC in collaboration with RTL Develop Conformal based ECO flows with an aim to address ALL ECOs rapidly.. Develop flows for rapid uarch prototyping in conjunction with RTL. Deploy power and physical aware synthesis flows. Work with 3rd party vendor resources and coordinate their work. Continuously work on improving flow consistency and efficiency in the context of multiple product lines. Required Qualifications Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience Experience with EDA flow using Cadence/Synopsys/Mentor tools for frontend flows, like Genus, Fusion Compiler, Design Compiler, Conformal, Formality. Experience with hierarchical design and modelling Hands-on experience in convergence of high-frequency and low power designs. Knowledge of static timing analysis, defining constraints and exceptions and low power design techniques (isolation, level shifting, power switches..). Experience with low power implementation typical in industry, Excellent scripting skills in TCL, shell and python. Desired Qualifications & Experience Requirements Experience in design space exploration for maximizing PPA using synthesis flows. Doing feasibility level sweeps to figure out optimal design build points. Proficiency with industry-grade physical design flow. Definition of design constraints. Knowledge of technology fundamentals and its implications to physical design We offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate. Why Join Efficient? Efficient offers a competitive compensation and benefits package , including 401K match, company-paid benefits, equity pro