Substrate Layout Design Engineer

About Eridu Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability. The company’s solutions and value proposition have been widely validated by leading hyperscalers. Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems. Visit our website eridu.ai to learn more. Position Overview We are seeking an experienced Substrate Layout Design Engineer to support the development of an advanced multi-die organic based flip chip module that integrates multiple dies in a chiplet format within a high-density, high-performance substrate. This role focuses on physical layout of the substrate using Siemens Xpedition tool, routing feasibility, and co-design alignment with floor planning, mechanical, and system constraints. Additionally, design of organic based substrates for SMT attachment with multilayer ABF based stack up. The successful candidate will collaborate closely with package integration, signal/power integrity, and system mechanical teams to ensure successful layout implementation and manufacturability for a complex multi-chip package. Responsibilities Drive physical layout of high-density substrate designs for advanced multi-die packages, including planning of bump maps, netlist alignments, escape/breakout routing, via structures, and layer stack-up definition for optimum performance of signal and power connectivity. Assess routing feasibility in a co-design environment, considering die floorplans, netlist, IO bump placement, and mechanical constraints at both the component and system levels. Collaborate with system architects, packaging engineers, ASIC, SI/PI, and mechanical teams to align on floor planning strategies and package mechanical outline and structure. Optimize signal, power, and ground integrity through intelligent routing, layer usage, and design constraint enforcement. Execute DRC, DFM, and manufacturing rule checks to ensure design readiness for fabrication and assembly. Generate and release final design packages and interface with substrate vendors for fabrication and manufacturability. Support technical reviews of substrate layouts and iterate with internal and external stakeholders on design improvements for optimum performance. Qualifications 8+ years of experience in advanced substrate layout for high-performance IC packaging, with direct involvement in multi-die or chiplet-based designs. Proven expertise in organic substrate layout with high routing density, fine-pitch bump escape, and constrained layer stack-ups. Experience in PCB design layout and schematic. Strong understanding of co-design methodology, including interactions between floorplan, substrate layout, and system mechanical boundaries. Proficient with Siemens Xpedition, Allegro Cadence APD, design tools. Familiarity with SI/PI design principles and how org