ASIC Architect

About Eridu Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability. The company’s solutions and value proposition have been widely validated by leading hyperscalers. Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems. Visit our website eridu.ai to learn more. Position Overview We are looking for a highly experienced ASIC Architect to contribute to the definition and implementation of Eridu's industry leading networking products. This is a unique opportunity to help shape the future of AI Networking. Responsibilities Work closely with the CTO to translate high-level system requirements and customer use cases into detailed architecture and functional specifications. Collaborate with chip and system microarchitects to align ASIC architecture with system-level goals for throughput, latency, and power efficiency. Guide modeling and feasibility analysis of packet flow behavior through the switch datapath to validate architectural choices, including throughput, latency, power and area efficiencies. Work closely with RTL, Verification, Physical Design and Firmware teams to ensure seamless design implementation and handoff. Guide integration of internal and external IPs (e.g. MAC, PCIe, SerDes) into the broader architecture. Drive interface requirements. Participate in design reviews, performance modeling, test and verification strategies and architectural trade-off analysis. Contribute to post-silicon validation for performance and correctness. Investigate and resolve complex issues related to ASIC data path, working closely with cross-functional teams including hardware engineers, firmware developers, and system architects. Qualifications MSEE with 10+ years of experience , preferably in networking ASIC architecture and design. Candidates with experience in related areas of computer and parallel processing architectures – in particular, complex memory crossbars, buffering schemes, scheduling algorithms and high-speed datapaths – are also highly desired. A deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications, or a willingness to become expert. Demonstrated expertise in microarchitecture definition, performance modeling, and trade-off analysis. Capability to develop Architecture behavioral models is highly desired. Experience working across the ASIC development lifecycle, from concept through productization. Experience in high-speed I/O integration (e.g., PCIe Gen5/Gen6, SerDes) and Software Control Plane interface architecture is highly desirable. Understanding of physical design implications on packet processing and buffering architecture (e.g., timing, area, power). Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting