Architecture & Performance Modeling Engineer

About Eridu Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability. The company’s solutions and value proposition have been widely validated by leading hyperscalers. Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems. Visit our website eridu.ai to learn more. Position Overview We are seeking a highly skilled and visionary Performance Modeling Engineer to drive the definition, development, and application of Eridu AI’s architectural and performance modeling infrastructure. In this role, you will set the direction for modeling efforts that directly influence our ASIC architecture and microarchitecture (uArch) designs. You will collaborate closely with system architects, chip designers, and cross-functional teams to evaluate design trade-offs, identify bottlenecks, and deliver actionable insights that shape the future of large-scale AI networking. This is an opportunity to establish a modeling strategy at the cutting edge of AI hardware while working alongside a team of talented performance engineers. Responsibilities Participate in the development and deployment of high-level performance models for networking devices to guide architectural decisions. Define modeling methodologies and frameworks that ensure consistency, accuracy, and scalability across projects. Partner closely with ASIC architects and uArch teams to evaluate trade-offs in throughput, latency, power, and area. Drive performance analysis and bottleneck identification to inform and influence architecture and design choices. Oversee the creation and validation of structural and traffic models to explore real-world workloads and system scenarios. Establish and champion best practices for performance modeling, documentation, and reporting. Communicate modeling results, insights, and recommendations to senior technical and leadership stakeholders. Qualifications MSEE/PhD in Electrical Engineering, Computer Engineering, or a related field with 10+ years of relevant industry experience. Proven track record of technical leadership in performance modeling or architecture for ASICs, SoCs, or networking systems. Deep expertise in networking protocols such as Ethernet and PCIe. Proficiency in modeling languages and tools, including C, C++, Python, and scripting environments. Strong background in FPGA/ASIC design flows, including synthesis, simulation, and verification tools (e.g., Verilog, VHDL, Synopsys, Cadence). Demonstrated ability to drive architectural discussions and influence design trade-offs through modeling insights. Excellent analytical and problem-solving abilities with a data-driven approach. Strong communication skills with the ability to present complex technical information clearly and persuasively. Why Join Us? At Eridu, you’ll have the opportunity to shape the f